1. Field of the Invention
The present invention relates to logic arrays and fabrication method for custom integrated circuit
2. Discussion of Background Art
Semiconductor manufacturing is known to improve device density in exponential manner over time, but such improvements do come with a price. The cost of mask set required for each new process technology has been increasing exponentially. In addition, the minimum fabrication quantity due to the increases of wafer size has also increased exponentially at the same time.
These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse markets therefore making the increased cost of product development and reduction of manufacturing flexibility very hard to accommodate.
Custom Integrated Circuits can be segmented into two groups. The first group includes devices that have all their layers custom made. The second group includes devices that have at least some generic layers used across different custom products. Well known examples of the second kind are Gate Arrays, which use generic layers for all layers up to contact layer, and FPGAs which utilize generic layers for all their layers. This second group of custom integrated circuits is also sometimes called semi-custom devices due to their broader applicability. The generic layers in such devices are mostly a repeating pattern structure in array form.
The use of generic layers across multiple application provides saving for the individual custom product with respect to the cost of masks and economies of scale. In 1996 Chip Express of Santa Clara, Calif., introduced a logic array called CX2000 that utilized a base logic cell equivalent to about 4 logic gates. At a later time Lightspeed Semiconductor of Sunnyvale, Calif., introduced their 3G Modular Array product family. These more advanced logic arrays use generic layers, comprising mostly repeating pattern, also for some of the metal layers such as contact, Metal-1, Via-1 and Metal-2. These types of logic arrays are sometime called Module Arrays and require less custom layers. A very advanced Module Array technology was introduced by eASIC of San Jose, Calif., in September 2000.
That Module Arrays uses generic layers such as Metal-1 and Metal-2 to define the logic array, in conjunction with generic layers such as Metal-3 and Metal-4 to provide a generic connectivity fabric. The generic connectivity fabric comprises of repeating patterns that are also structured in array form. Such arrangement allows to further reduce the number of custom layers required for design customization. eASIC technology, as described in U.S. Pat. No. 6,331,790 is going further toward the goal minimizing the number of custom masks and requires only a single custom via mask.
The logic array technology is based on a generic fabric that is customized for a specific design during the customization stage. As designs tend to be highly variable in the amount of logic and memory each one needs, vendors of logic array create product families with a number of Master Slices covering a range of logic and memory size options. Yet, it is always a challenge to come up with minimum set of Master Slices that will provide a good fit for maximal number of designs.
U.S. Pat. No. 4,733,288 issued to Sato Shinji Sato in March 1988, discloses a method “to provide a gate-array LSI chip which can be cut into a plurality of chips, each of the chips having a desired size and a desired number of gates in accordance with a circuit design.” The prior art in the references cited presents few alternative methods to utilize generic structure for a different size of custom devices.
The array structure fits the objective of variable sizing. The difficulty to provide variable-sized devices is due to the need of providing I/O cells and associated pads to connect the device to the package. To overcome this limitation Sato suggests a method where I/O could be constructed from the transistors that are also used for the general logic gates. A similar approach was also suggested by Anderson. U.S. Pat. No. 5,217,916 issued to Anderson et al. on Jun. 8, 1993, discloses a configurable gate array free of predefined boundaries—borderless—using transistor gate cells, of the same type of cells used for logic, to serve the input and output function. Accordingly, the input and output functions may be placed to surround the logic array sized for the specific application. This method presents a severe limitation on the I/O cell to use the same transistors as used for the logic and would not allow the use of higher operating voltage for the I/O.
U.S. Pat. No. 5,721,151 issued to Padmananabhan et al. on Feb. 24, 1998, suggests the use of contiguous number of micro-arrays each surrounded by an I/O array—conventionally structured—but having these micro-arrays interconnected to form ‘composite array’. Padmananabhan suggests few ways to use the I/O that end up internal in the ‘composite array’ such as to drive signals from one micro-array to another or to be bonded using bump and flip-chip technology. The method suggested by Padmananabhan has some severe limitations. For example having each micro-array surrounded by an I/O array results in the micro-array being relatively large to allow for a reasonable ratio of logic transistors to I/O transistors. That results in 151′ suggestion to have “unused macro-arrays being cut away and discarded”
The current invention seeks to overcome many of the prior-art limitations. It is known in the art that I/O and pads do not need to be at the edge of the semiconductor device. Semiconductor devices could be using the flip chip or C-4 (controlled collapse chip connection) technology described in U.S. Pat. Nos. 3,401,126 and 3,429,040 by Miller that had been used for over 30 years in IBM's mainframe computer modules. In these approaches the bonding pads are deployed in an area array over the surface of the chip known as area bonding and may use I/O cells known as area I/O placed near the area pads. Flip Chip packaging is known in the art to use an additional final metal layer known as the redistribution layer, to allow proper distribution of the device I/O to the area pads.